The present invention relates to a semiconductor integrated circuit device and to a technique for manufacturing the same; and, more particularly, the invention relates to a device isolation structure for forming fine or micro MISFETs (Metal Insulator Semiconductor Field Effect Transistors) and a technique effective for application to a forming process thereof.
With scale-down and high integration of semiconductor chips or elements, the introduction of a shallow groove isolation (SGI), of a type in which an insulating film is embedded inside each groove defined in a silicon substrate, is proceeding to provide a device isolation structure that serves as an alternative to a local oxidization of silicon (LOCOS) method.
The above-described shallow groove isolation is considered to be advantageous from the point of view of ensuring sub-threshold characteristics and reduction in junction leakage and a backgate effect, as compared with the LOCOS method, because (a) the device isolation interval or space can be reduced, (b) it is easy to control the film thickness for device isolation and set a field reverse voltage, and (c) an inversion preventive layer can be separated from a diffused layer and a channel region by separately implanting an impurity in side walls of the inside of each groove and the bottom thereof.
A common method for forming the shallow groove isolation is as follows: First of all, a silicon substrate is subjected to thermal oxidation and a thin silicon oxide film is formed on the surface thereof. Thereafter, a silicon nitride film is deposited thereabove by a CVD (Chemical Vapor Deposition) method. Next, each silicon nitride film lying in a device isolation region is removed by dry etching using a photoresist film as a mask. Thereafter, trenches or grooves are defined in the substrate by dry etching with the silicon nitride films being left in each active region as masks.
Next, a thick silicon oxide film is deposited on the substrate, including the interiors of the grooves, by the CVD method. Thereafter, the substrate is subjected to a thermal process, and the silicon oxide films embedded inside the grooves are elaborately densified. Thereafter, the silicon oxide films above the silicon nitride films are removed by a polishing process, such as etchback or chemical mechanical polishing (CMP) or the like, and the unnecessary silicon nitride films are then removed, whereby shallow groove isolations are completed. Shallow groove isolations are discussed, for example, in Japanese Laid-Open Patent Application No. Hei 02-260660, No. Hei 04-303942, No. Hei 08-97277 etc.
The present inventors have found that thinning (local thinning) occurs in that a gate oxide film formed on the surface of the substrate corresponding to each active region would locally be thinned at a peripheral portion of the active region, and a phenomenon (called a MOS-IV kink characteristic) in which a drain current tends to flow in response to a low gate voltage, have developed in the above-described device isolation structure. As a measure for solving these problems, the present inventors have considered a technique for rounding the peripheral portion of the active region (effecting round processing on it).
As a result of examining this approach, the present inventors have found that the (round processing) technique for rounding the peripheral portion of each active region, after the grooves are defined in the substrate, has a problem in that, since it requires a high-temperature thermal oxidizing process, a thermal oxide film formed on an inner wall of each groove due to the thermal oxidizing process at the time of round processing tends to grow to the active region side, thereby reducing the size of the active region, and, hence, this provides a hindrance to high integration and scale down of each MISFET.
Namely, a problem arises in that, when the round processing (round) is insufficient, thinning (local thinning) occurs in which a gate oxide film is thinly formed at a peripheral portion of each pointed active region upon oxidation for forming the gate oxide film, and a variation in the threshold voltage of each MISFET is produced due to a MOS-IV kink characteristic. It is necessary to sufficiently effect round processing (round) as an effective measure. However, when sufficient round is applied to the peripheral portion of the active region, the active region (particularly, in the direction of a gate width of each MISFET) becomes narrow. Therefore, the size (particularly, the gate width of the MISFET) of the active region cannot be ensured, and the semiconductor elements cannot be scaled down. In addition, this provides a hindrance to the desire for the width of each shallow groove isolation to be miniaturized and the semiconductor elements to be scaled down, so as to be brought into high integration.
An object of the present invention is to provide a technique that is capable of providing an advancement in the scale-down of MISFETS.
Another object of the present invention is to provide a technique that is capable of promoting the scale-down of the width of each shallow groove isolation.
The above and other objects and novel features of the present invention will become apparent from the description provided in the present specification from and the accompanying drawings.
Summaries of typical aspects and features of the invention disclosed in the present application will be described briefly as follows:
(1) A semiconductor integrated circuit device according to the present invention comprises a plurality of active regions each having an island-shaped plane pattern whose periphery is surrounded by shallow groove isolations, which are disposed on a main surface of a substrate so as to have predetermined intervals in a first direction, and semiconductor elements formed in the plurality of active regions, and wherein the sum of the width of each active region extending in the first direction and the space defined between the adjacent active regions constitutes a minimum pitch in the first direction, and the width of each active region in the first direction is set larger than one-half the minimum pitch.
(2) In a semiconductor integrated circuit device according to the item 1, the half of the minimum pitch is a minimum processing size determined according to a resolution limit of photolithography.
(3) In a semiconductor integrated circuit device according to the item 1 or 2, the semiconductor elements are respectively coupled to interconnections disposed so as to have predetermined intervals, and the width of each interconnection and the space between the adjacent interconnections are respectively set to the minimum pitch.
(4) A semiconductor integrated circuit device according to the present invention comprises a plurality of active regions each having an island-shaped plane pattern whose periphery is surrounded by shallow groove isolations, which are disposed on a main surface of a substrate so as to have predetermined intervals in a first direction, and semiconductor elements formed in the plurality of active regions, and wherein the sum of the width of each active region extending in the first direction and the space defined between the adjacent active regions is set to twice a minimum processing size determined according to a resolution limit of photolithography, the width of each active region is greater than or equal to the minimum processing size and the space defined between the adjacent active regions is less than or equal to the minimum processing size.
(5) In a semiconductor integrated circuit device according to the item 2, 3 or 4, the semiconductor elements are respectively coupled to interconnections disposed so as to have predetermined intervals, and the width of each interconnection and the space between the adjacent interconnections are respectively set to the minimum processing size determined according to the resolution limit of photolithography.
(6) In a semiconductor integrated circuit device according to the item 3 or 5, each of the semiconductor elements constitutes a memory cell, and each of the interconnections constitutes a word line or a bit line connected to the memory cell.
(7) In a semiconductor integrated circuit device according to any of the items 1 to 6, a peripheral portion of each active region whose periphery is surrounded by the shallow groove isolations, is shaped in the form of a section with a convex round.
(8) In a semiconductor integrated circuit device according to any of the items 1 to 7, the thickness of a gate insulating film of each semiconductor element formed on the surface of the substrate in each active region is equal in central and peripheral portions of the active region.
(9) In a semiconductor integrated circuit device according to any of the items 1 to 8, the semiconductor elements formed in each active region are comprised of MISFETs respectively, the MISFETs are memory cell selection MISFETs each of which constitutes part of each memory cell in a DRAM, and a capacitative element which constitutes another part of the memory cell in the DRAM, is connected in series with the memory cell selection MISFET.
(10) A method of manufacturing a semiconductor integrated circuit device, according to the present invention, comprises the following steps of:
forming silicon nitride films on a main surface of a substrate so that the sum of the width of each silicon nitride film extending in a first direction and the space defined between the adjacent silicon nitride films extending in the first direction constitutes a minimum pitch in the first direction,
forming side wall spacers on side walls of each silicon nitride film and thereafter defining grooves in the substrate in self-alignment with the side wall spacers,
removing the side wall spacers and thereafter oxidizing the substrate to thereby effect round processing on the surface of the substrate, and forming an insulating film on the substrate including the interiors of the grooves and thereafter removing the insulating film lying outside the grooves, and embedding the insulating film in the grooves to thereby define shallow groove isolations for defining each active region.
(11) A method of manufacturing a semiconductor integrated circuit device, according to the present invention, comprises the following steps of:
selectively forming silicon nitride films on a main surface of a substrate,
forming side wall spacers on side walls of the silicon nitride films respectively and thereafter etching the substrate in self-alignment with the side wall spacers to thereby define grooves in the substrate in each device isolation region,
removing the side wall spacers and thereafter subjecting the substrate to thermal oxidation to thereby effect round processing on the surface of the substrate at a peripheral portion of each active region, and
forming an insulating film on the substrate including the interiors of the grooves, thereafter removing the insulating film lying over each silicon nitride film and embedding the insulating film in the grooves to thereby define shallow groove isolations.
(12) A method of manufacturing a semiconductor integrated circuit device, according to the present invention, comprises the following steps of:
selectively forming silicon nitride films on a main surface of a substrate,
forming side wall spacers on side walls of the silicon nitride films respectively and thereafter etching the substrate in self-alignment with the side wall spacers to thereby define grooves in the substrate in each device isolation region,
removing the side wall spacers and thereafter subjecting the substrate to thermal oxidation to thereby effect round processing on the surface of the substrate at a peripheral portion of each active region,
etching each silicon nitride film to thereby recess a peripheral portion of each silicon nitride film to the center side of the active region, and
forming an insulating film on the substrate including the interiors of the grooves, thereafter removing the insulating film lying over each silicon nitride film and embedding the insulating film in the grooves to thereby define shallow groove isolations for defining the active regions.
(13) in a method of manufacturing a semiconductor integrated circuit device, according to the item 12, the etching for recessing the peripheral portion of the silicon nitride film to the center side of the active region is isotropic etching.
(14) A method of manufacturing a semiconductor integrated circuit device, according to any of the items 10 to 13 further includes a step of subjecting the substrate to thermal oxidation after the insulating film is embedded in the grooves to thereby form a gate insulating film for each MISFET on the surface of the substrate in each active region and then form each gate electrode for the MISFET on the gate insulating film.
(15) A method of manufacturing a semiconductor integrated circuit device, according to the item 14 further includes a step of forming a silicon oxide film on the surface of the substrate in each active region prior to the gate insulating film forming step, a step of implanting impurity ions in the substrate through the silicon oxide film, a step of subjecting the substrate to a thermal process to diffuse the impurity ions, thereby forming wells in the substrate, and a step of etching the surface of the substrate to thereby remove the silicon oxide film.
(16) In a method of manufacturing a semiconductor integrated circuit device, according to the item 14, the gate electrodes for the MISFETs extend across the active regions and the shallow groove isolations.
(17) In a method of manufacturing a semiconductor integrated circuit device, according to the item 14, the MISFETs are respectively memory cell selection MISFETs each of which constitutes part of each memory cell in a DRAM.
(18) In a method of manufacturing a semiconductor integrated circuit device, according to any of the items 10 to 17, each silicon nitride film has a slender and island-shaped plane pattern, and the size of each silicon nitride film in the first direction and the space defined between the silicon nitride films adjacent to each other in the first direction are respectively equal to a minimum size determined according to a resolution limit of photolithography.
(19) In a method of manufacturing a semiconductor integrated circuit device, according to the item 18, the gate electrodes for the MISFETs linearly extend along a second direction intersecting the first direction of each active region at the same widths and same spaces, and the widths and spaces are respectively equal to a minimum size determined according to a resolution limit of photolithography.
(20) In a method of manufacturing a semiconductor integrated circuit device, according to any of the items 10 to 19, the side wall spacers comprise a silicon oxide film.
(21) In a method of manufacturing a semiconductor integrated circuit device, according to any of the items 10 to 20, the thickness of each side wall spacer ranges from 5 nm to 40 nm.
(22) A method of manufacturing a semiconductor integrated circuit device, according to any of the items 10 to 21 further includes a step of forming the side wall spacers on the side walls of the silicon nitride films and thereafter implanting impurity ions in the neighborhood of the surface of the substrate including regions below the side wall spacers prior to the step of defining the grooves in the substrate.
(23) In a method of manufacturing a semiconductor integrated circuit device, according to any of the items 10 to 22, when the substrate is etched in self-alignment with the side wall spacers to define the grooves, the neighborhood of the surface of the substrate is first isotropically etched to thereby isotropically etch the neighborhood of the surface of the substrate in the regions below the side wall spacers, and the substrate is then anisotropically etched to define the grooves.
(24) In a method of manufacturing a semiconductor integrated circuit device, according to any of the items 10 to 23, the neighborhood of the surface of the substrate in the regions below the side wall spacers is isotropically etched after the removal of the side wall spacers, and the substrate is then subjected to thermal oxidation to thereby effect round processing on the surface of the substrate at the peripheral portion of each active region.
(25) In a method of manufacturing a semiconductor integrated circuit device, according to any of the items 10 to 24, the thermal oxidation for effecting the round processing on the surface of the substrate is performed plural times in parts.
(26) In a method of manufacturing a semiconductor integrated circuit device, according to any of the items 10 to 25, the inner walls of the grooves are etched prior to the step of embedding the insulating film in the grooves after the round processing of the surface of the substrate, whereby silicon oxide films formed on inner walls of the grooves by the thermal oxidation at the round processing are removed or thinned.
(27) In a method of manufacturing a semiconductor integrated circuit device, according to any of the items 10 to 26, the substrate is subjected to a thermal process after the insulating film is embedded in the grooves or in the course thereof to thereby densify the insulating film.
(28) A method of manufacturing a semiconductor integrated circuit device, according to the present invention, comprises the following steps of:
(a) selectively forming silicon nitride films on main surfaces of first and second regions of a substrate,
(b) forming first side wall spacers on side walls of the silicon nitride films left on the substrate,
(c) covering the first region of the substrate with a first photoresist film and etching the first side wall spacers in the second region, thereby forming thin second side wall spacers thicker than the first side wall spacers on the side walls of the silicon nitride films in the second region,
(d) removing the first photoresist film and thereafter etching the substrate in self-alignment with the first side wall spacers and second side wall spacers, thereby defining grooves in the substrate,
(e) removing the first side wall spacers and second side wall spacers and thereafter subjecting the substrate to thermal oxidation, thereby effecting round processing on the surface of the substrate at a peripheral portion of each active region, and
(f) forming an insulating film on the substrate including the interiors of the grooves, thereafter removing the insulating film above each silicon nitride film and embedding the insulating film in the grooves, thereby forming shallow groove isolations for defining each active region.
(29) A method of manufacturing a semiconductor integrated circuit device, according to the item 28, further includes, after the step (f), steps of:
(g) removing the silicon nitride films and performing an etching process for reducing a step between the surface of the substrate corresponding to the active region and the surface of the insulating film lying within each shallow groove isolation,
(h) subjecting the substrate to thermal oxidation to thereby form a first gate oxide film for a first MISFET on the surface of the substrate in the active region,
(i) covering the second region of the substrate with a second photoresist film and etching the surface of the first region of the substrate, thereby removing the first gate oxide film in the first region, and
(j) removing the second photoresist film and thereafter subjecting the substrate to thermal oxidation, thereby forming a second gate oxide film for a second MISFET on the surface of the first region of the substrate.